Crosstalk Peak Overshoot Analysis of VLSI Interconnects
*D. Rajesh Setty
Y. Mallikarjuna Rao
*Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, India
Santhiram Engineering College, Nandyal, Andhra Pradesh-518501, India
Abstract: As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.
Keywords: CMOS inverter, Crosstalk, Interconnect, Power dissipation.
- Venkataiah, N. Ramanjaneyulu, Y. Mallikarjuna Rao, V. N. V. Satya Prakash, M. K. Linga Murthy, N. Sreenivasa Rao “Design and performance analysis of buffer inserted on‑chip global nano interconnects in VDSM technologies,” Nanotechnology for Environmental Engineering, May,2022. https://doi.org/10.1007/s41204-022-00249-x
- Sulochana, C. Venkataiah, Sunil Agrawal & Balwinder Singh, “Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic”, IETE Journal of Research, December 2020. https://doi.org/10.1080/03772063.2020.1864235
- Venkataiah, V.N.V. Satya Prakash, K. Mallikarjuna and T. Jayachandra Prasad, “Investigating the effect of chirality, oxide thickness, temperature and channel length variation on a threshold voltage of MOSFET, GNRFET, and CNTFET,” Journal of mechanics of continua and mathematical sciences, pp 232-244, September 2019. https://doi.org/10.26782/jmcms.spl.3/2019.09.00018.
- Vijay Rao Kumbhare, Punya Prasanna Paltani, C. Venkataiah, and Manoj Kumar Majumder, “Analytical Study of Bundled MWCNT and Edged-MLGNR Interconnects: Impact on Propagation Delay and Area,” IEEE Transactions on Nanotechnology, vol. 18, pp.606-610, June 2019. https://doi.org/10.1109/TNANO.2019.2920679.
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Insertion of optimal number of repeaters in pipelined nano interconnects for transient delay minimization,” Circuit systems and signal processing, February 2019. https://doi.org/10.1007/s00034-018-0876-7
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “FDTD algorithm to achieve absolute stability in performance analysis of SWCNT interconnects,” Journal of computational electronics, June 2018. https://doi.org/10.1007/s10825-017-1125-1
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Crosstalk induced performance analysis of single walled carbon nanotube interconnects using stable finite difference time domain model,” Journal of nanoelectronics and optoelectronics, vol. 12, pp.1-10, June 2018. https://doi.org/10.1166/jno.2017.2300
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Signal integrity analysis for coupled SWCNT interconnects using stable recursive algorithm,” Microelectronics Journal, vol. 74, pp.13-23, April 2018. https://doi.org/10.1016/j.mejo.2018.01.012
- V.S. Reddy, C.Venkataiah, V.R.Kumar, S.Maheswaram, N. Jains, S.D. Gupta and S.K. Manhas, “Design and simulation of CNT based nano-transistor for greenhouse gas detection,” Journal of nanoelectronics and optoelectronics, vol. 12, pp.1-9, April 2018. https://doi.org/10.1166/jno.2017.2133
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Impact of Supply and Threshold Voltage Scaling on Performance of Cu and CNT Interconnects,” International Journal of Pure and Applied Mathematics, vol.118, no. 5, pp. 117-126, July 2018.
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Effect of line parasitic variations on delay and energy of global on-chip VLSI Interconnects in DSM Technology,” International conference on Micro-electronics, Electromagnetics and Telecommunications (ICMEET), Lecture Notes in Electrical Engineering 434, pp. 221-228, July 2018. https://doi.org/10.1007/978-981-10-4280-5_23.
- Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Effect of Interconnect parasitic variations on circuit performance parameters,” IEEE International conference on communication and electronics systems (ICCES), Coimbatore, India, pp.289-292, October 2016, 978-1-5090-1066-0/16/$31.00 ©2016 IEEE
- Venkataiah, M. Tejaswi, “A Comparative Study of Interconnect Circuit Techniques for Energy Efficient on-Chip Interconnects,” International Journal of Computer Applications, vol.109, no. 4, January 2015.
- Manjula jayamma, Y. Mallikarjuna Rao, N. Ramanjaneyulu, Anchula Sathish, “Delay and power efficient technique for VLSI interconnects,” Research and applications: emerging technologies, vol. 4, Issue 3, HBRP publication, pp.1-7, December 2022. https://doi.org/10.5281/zenodo.7475855
- Manjula jayamma, Y. Mallikarjuna Rao, N. Ramanjaneyulu, Anchula Sathish, “Crosstalk analysis of SLGNR based VLSI interconnects,” Recent trends in analog design and digital devices, vol. 5, Issue 3, HBRP publication, pp.1-7, December 2022. https://doi.org/10.5281/zenodo.7472762
- Manjula jayamma, Y. Mallikarjuna Rao, N. Ramanjaneyulu, Anchula Sathish, “Delay analysis of VLSI interconnects for high speed applications,” Journal of VLSI Design and signal processing, vol.8, Issue 3, MAT Journals, pp.23-28, December 2022.
- Venkataiah, V. N. V. Satya Prakash, V.Neeraja “Performance Analysis of Boostable Repeater in Different VLSI Interconnects and Applications,” International Journal of Advanced Research in Computer and Communication Engineering, vol. 3, Issue 11, November 2014.
- Venkataiah, C.Vijaya Bharathi, M.Narasimhulu, “Power Efficient Weighted Modulo 2n+1 Adder,” International Journal of Computer & Organization Trends, vol.3, Issue 11, Dec 2013.
- Venkata Siva Reddy, C.Venkataiah “Design of Adder in Multiple Logic Styles for Low Power VLSI,” International Journal of Computer Trends and Technology, vol.3, issue 3, June, 2012.
- Manjula jayamma, N. Ramanjaneyulu, Anchula Sathish, Y. Mallikarjuna Rao, “Analysis of crosstalk in GNR based global interconnects,” Journal of VLSI Design and its Advancement, vol. 5, Issue 3, HBRP publication, pp.1-8, December 2022. https://doi.org/10.5281/zenodo.7431946
- Manjula jayamma, N. Ramanjaneyulu, Anchula Sathish, Y. Mallikarjuna Rao, “Crosstalk analysis of on-chip VLSI interconnects,” International Journal of Emerging Research in Engineering, Science, and Management, vol. 1, Issue 4, pp.06-11, Oct-Dec 2022. https://doi.org/10.58482/ijeresm.v1i4.2
- Manjula jayamma, N. Ramanjaneyulu, Anchula Sathish, Y. Mallikarjuna Rao, “Analysis of crosstalk in coupled on-chip VLSI interconnects,” Journal of advancement in communication systems, vol. 5, issue 3, HBRP publication, pp.1-8, December, 2022. https://doi.org/10.5281/zenodo.7413063