International Journal of Emerging Research in Engineering, Science, and Management
Vol. 2, Issue 1, pp. 08-12, Jan-Mar 2023.
https://doi.org/10.58482/ijeresm.v2i1.2
This work is licensed under a Creative Commons Attribution 4.0 International License.
Crosstalk Peak Overshoot Analysis of VLSI Interconnects
*C. Venkataiah
*D. Rajesh Setty
*N. Ramanjaneyulu
Y. Mallikarjuna Rao
*Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, India
Santhiram Engineering College, Nandyal, Andhra Pradesh-518501, India
Abstract: As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.
Keywords: CMOS inverter, Crosstalk, Interconnect, Power dissipation.
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