International Journal of Emerging Research in Engineering, Science, and Management
Vol. 3, Issue 3, pp. 13-19, July-Sep 2024.
https://doi.org/10.58482/ijeresm.v3i3.3

Optimized Multiplier Architectures for Enhanced Performance and Efficiency in MAC Units

G Priyanka

 N Gireesh

S Hemachandra

Research Scholar, Department of ECE, School of Engineering, Mohan Babu University, Tirupati

Professor, Department of ECE, School of Engineering, Mohan Babu University, Tirupati

Dean, IIR & Professor, Department of EEE, School of Engineering, Mohan Babu University, Tirupati

Abstract: This paper investigated the performance of Vedic multipliers in a 32-bit Multiplier-Accumulator Unit (MAC) by comparing Urdhva Tiryakbhyam and Nikhilam Sutras with various adder architectures. The goal was to identify the optimal combination of speed and resource efficiency. Urdhva Tiryakbhyam with CLA emerged as the fastest option, achieving a minimal delay of 0.709 ns. However, this came at the cost of higher resource utilization, measured in Logic Look-Up Tables (LUTs). Conversely, Nikhilam implementations generally required fewer LUTs, making them more resource-efficient, but they exhibited slightly slower performance. CLA consistently delivered the best delay for both Vedic multiplier types among the adder architectures. All the explored configurations are viable for practical implementation on Xilinx ISE 14.7. The key takeaway is that the choice between Urdhva Tiryakbhyam and Nikhilam and the specific adder architecture hinges on the application’s priorities.

Keywords: Deep Learning Model, MAC, Vedic Multipliers, Wallace Tree.

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